1. Field of the Invention
The present invention generally relates to a receiver used in a communication system employing the CDMA (code division multiple access) scheme, and particularly relates to a path-search circuit used in the receiver wherein the path-search circuit establishes synchronization by detecting a peak (path timing) of a delay profile of a received signal, and maintains the synchronization.
2. Description of the Related Art
FIG. 15 is a block diagram showing a related-art path-search circuit.
A code-spreading modulated signal is received by an antenna, and is supplied to a QPSK modulator 102 via a band-bass filter 101. The QPSK modulator 102 demodulates the received signal, and supplies in-phase components and quadrature components to A/D converters 105 and 106 via low-pass filters 103 and 104, respectively. The demodulated signals are converted into digital signals comprised of X bits. XX upper bits of these X bits, for example, are input to a path-search circuit 107. Here, the digital signals having all the X bits may be input to the path-search circuit 107. Use of the XX upper bits of the X bits, however, can reduce circuit size while incurring almost no degradation in path-search accuracy.
The path-search circuit 107 includes received-signal-holding units 111 and 112 comprised of memories or the like, a write-control circuit 113, a read-control circuit 114, a code-generation circuit 115, matched filters 116 and 117, in-phase-summation circuits 118 and 119, a power-conversion circuit 120, a power-summation circuit 121, a write-control circuit 122, a read-control circuit 123, a delay-profile-holding unit 124 comprised of a memory or the like, and a path-timing-detection circuit 125.
The received-signal-holding units 111 and 112 hold in-phase components of the received signals and quadrature components of the received signals, and supply them to the matched filters 116 and 117, respectively. The matched filters 116 and 117 obtain correlation with de-spreading code sequences supplied from the code-generation circuit 115. Then, the in-phase-summation circuits 118 and 119 add together correlation values having small phase differences, and the power-conversion circuit 120 obtains electrical power through calculation of squares. The power is repeatedly added over predetermined time periods by the power-summation circuit 121 and the delay-profile-holding unit 124, so that an average over time sequence is obtained. The path-timing-detection circuit 125 detects a peak point of the delay profile to output a path-timing signal.
FIG. 16 is an illustrative drawing for explaining operation of a related-art matched filter. FIG. 16 shows a main portion of either one of the matched filters 116 and 117 shown in FIG. 15. As shown, the matched filter includes a received-signal register 131, a code register 132, multiplication units 133, and a summation circuit 134. This configuration corresponds to a case in which a spreading factor m is 256, and an over-sample ratio k relative to the chip rate is four.
When the received-signal register 131 receives a received-signal sequence comprised XX bits as described above, the received-signal register 131 may be configured as a shift register having a 4-bit-parallel-shift configuration and comprised of 1024 stages in total (m×k=1024). The code register 132 is then a shift register having 256 stages (m=256), and there are multiplication units 133 as many as 256 to make up a multiplication circuit. A received-signal sequence r(t) corresponding to every fourth stage of the received-signal register 131 is multiplied by the de-spreading-code sequence c(t) corresponding to every stage of the code register 132. Results of multiplications obtained as outputs of the 256 multiplication units 133 are added together by the summation circuit 134, thereby producing a correlation value at the given timing. The received-signal sequence r(t) is shifted at high speed in the received-signal register 131, and is multiplied by the de-spreading-code sequence, with the results of multiplications being summed again by the summation circuit 134. In this manner, a correlation-value sequence y(t) is obtained. A peak point of a delay profile that is a time average of the correlation-value sequence y(t) is then obtained as a path timing.
FIGS. 17A through 17D are illustrative drawing for explaining detection of correlation values in received signals that are diffused by use of identical codes.
In the space-diversity scheme using a plurality of antennas or in a system having antennas for respective sectors, it is the most general practice to provide receiver units including path-search circuits such that the path-search circuits correspond to the respective antennas. This configuration has a drawback in that the circuit size increases in proportion to the number of antennas. In order to facilitate shared use, a single circuit may be used in a time-divided fashion. For example, a signal received by a first antenna and a signal received by a second antenna have different phases and amplitudes, and are supplied to the one and same received-signal register of a matched filter on a time-divided basis, thereby outputting a correlation value.
FIG. 17A shows a situation in which the first symbol S11 of the signal received by the first antenna is input to the received-signal register. The input symbol is shifted thereafter, and the second symbol S12 is input to the received-signal register as shown in FIG. 17B. The first symbol S11 is multiplied by a de-spreading code of the first symbol S11 stored in the code register, and a result of the multiplication is summed together by the summation circuit to produce a correlation-value sequence having a length of one symbol.
FIG. 17C shows a situation in which the signal received by the second antenna is input to the received-signal register. When the first symbol S21 is input to the received-signal register, it is necessary to make sure that the preceding signals corresponding to the first antenna do not affect correlation computation for the second antenna signal. FIG. 17D shows a situation in which the first symbol S12 of the signal received by the second antenna is input to the received-signal register. From this instance, multiplication of the signal received by the second antenna by the de-spreading codes thereof stored in the code register proceeds, with the results of the multiplication being summed together by the summation circuit to produce a correlation value.
FIGS. 18A through 18D are illustrative drawings for explaining detection of correlation values having a length of two symbols for sequences of different codes.
Symbols S1 through S3 of a received-signal sequence are multiplied by a de-spreading code C1, and symbols S2 through S4 of the same received-signal sequence are multiplied by a de-spreading code C2 where the received-signal register and the code register are used in a time-divided fashion to produce correlation values. FIG. 18A shows a situation in which the first symbol S1 of the received signal is input to the received-signal register. This symbol and symbols coming thereafter are shifted, and the third symbol S3 is input as shown in FIG. 18B. Multiplication by the de-spreading code C1 of the symbol S1 stored in the code register is attended to, and the result of multiplication is summed together by the summation circuit to produce a correlation value of the symbol S1 having a length of two symbols.
As shown in FIG. 18C, the second symbol S2 is input to the received-signal register as an initial value, such that the preceding signals corresponding to the computation of a correlation value for the symbol S1 do not affect subsequent correlation computation. Further, a de-spreading code C2 is input to the code register. FIG. 18D shows a situation in which the second symbol S2 of the received signal is input to the received-signal register, and the de-spreading code C2 is input to the code register. From this instance, multiplication of the received signal by the de-spreading code stored in the code register proceeds, with the results of the multiplication being summed together by the summation circuit to produce a correlation value.
Path-search circuits are provided with matched filters as previously described, and need a received-signal register having the number of stages corresponding to the spreading factor m and the over-sample ratio k. Because of such a configuration, circuit size is relatively large. If matched filters are provided as many as there are a plurality of received-signal sequences, circuit size increases in proportion to the number of antennas.
If a received-signal register of a matched filter is to be used on a time-divided basis with respect to a plurality of signals received by respective antennas with an aim of reducing circuit size, the contents of the received signal register need to be all cleared as was described in connection with FIGS. 17A through 17D. Since there is a need to set initial values at every one of such turns, it is not possible to produce a continuous stream of correlation values. If a plurality of received signal sequences are temporarily held in storage, and the received-signal register has a received-signal sequence set therein in a parallel fashion, correlation values may be output as a continuous stream. Such a configuration requires complex circuit structure with regard to the means of holding received signals and the means of making parallel setting to the received-signal register. Even when a time-division scheme is used for different de-spreading codes as shown in FIGS. 18A through 18D, there is a need to make initial settings, thereby making it impossible to output a continuous stream of correlation values.
Accordingly, there is a need for a path-search circuit which can produce a continuous stream of correlation values without need for complex circuit structure when different received signal sequences or different code sequences are supplied.